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this product conforms to specifications per the terms of the ramtron ramtron international corporation standard warranty. the product has completed ramtron?s internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status. (800) 545-fram, (719) 481-7000 http://www.ramtron.com rev. 3.1 feb. 2009 page 1 of 22 fm3130 integrated rtc/alarm and 64kb f-ram features high integration device replaces multiple parts ? serial nonvolatile memory ? real-time clock (rtc) with alarm ? clock output (programmable frequency) 64kb ferroelectric nonvolatile ram ? internally organized as 8kx8 ? unlimited read/write endurance ? 45 year data retention ? nodelay? writes fast two-wire serial interface ? up to 1 mhz maximum bus frequency ? supports legacy timing for 100 khz & 400 khz ? rtc & f-ram controlled via 2-wire interface real-time clock/calendar ? backup current under 1 a ? seconds through centuries in bcd format ? tracks leap years through 2099 ? uses standard 32.768 khz crystal (12.5pf) ? software calibration ? supports battery or capacitor backup easy to use configurations ? operates from 2.7 to 3.6v ? 8-pin ?green? soic (-g) and tdfn (-dg) ? low operating current ? industrial temperature -40 c to +85 c ? underwriters laboratory (ul) recognized description the fm3130 integrates a real-time clock (rtc) and f-ram nonvolatile memory. the device operates from 2.7 to 3.6v. the fm3130 provides nonvolatile f-ram which features fast write speed and unlimited endurance. this allows the memory to serve as extra ram for the system microcontroller or conventional nonvolatile storage. this memory is truly nonvolatile rather than battery backed. the real-time clock (rtc) provides time and date information in bcd format. it can be permanently powered from external backup voltage source, either a battery or a capacitor. the timekeeper uses a common external 32.768 khz crystal and provides a calibration mode that allows software adjustment of timekeeping accuracy. pin configuration pin name function x1, x2 crystal connections acs alarm/calibration/sqwave sda serial data scl serial clock vbak battery-backup supply vdd supply voltage vss ground ordering information fm3130-g ?green?/rohs 8-pin soic FM3130-GTR ?green?/rohs 8-pin soic, tape & reel fm3130-dg ?green?/rohs 8-pin tdfn fm3130-dgtr ?green?/rohs 8-pin tdfn, tape & reel vss x1 vbak x2 1 2 3 4 5 6 7 8 vdd scl sda acs x1 x2 vbak vss vdd acs scl sda top view 1 2 3 4 8 7 6 5
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 2 of 22 figure 1. block diagram pin descriptions pin name type pin description x1, x2 i/o 32.768 khz crystal connection. when using an external oscillator, apply the clock to x1 and a dc mid-level to x2 (see crystal type section for suggestions). acs output alarm/calibration/squarewave: this is an open-drain output that requires an external pullup resistor. the alarm, calibration, and square wave functions all share this output. in alarm mode, this pin acts as the active-low alarm output. in calibration mode, a 512 hz square-wave is driven out. in squarewave mode, the user may select a frequency of 1, 512, 4096, or 32768 hz to be used as a continuous output. refer to table 3. control bit settings for acs pin to determine the bit settings for each mode. sda i/o serial data & address: this is a bi-directional line for the two-wire interface. it is open-drain and is intended to be wire-or?d with other devices on the two-wire bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling edges. a pull-up resistor is required. scl input serial clock: the serial clock line for the two-wire interface. data is clocked out of the part on the falling edge, and data into the device on the rising edge. the scl input also incorporates a schmitt trigger input for noise immunity. vbak supply backup supply voltage: a 3v battery or a large value capacitor. if no backup supply is used, this pin should be tied to v ss . the trickle charger is ul recognized and ensures no excessive current when using a lithium battery. vdd supply supply voltage. vss supply ground f-ram array 2-wire interface rtc v sw - + rtc re g isters special function registers x1 x2 lockout switched power rtc cal. battery backed nonvolatile acs alarm 512hz/s qw alarm scl sda vdd vbak
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 3 of 22 overview the fm3130 device combines a serial nonvolatile ram with a real-time clock (rtc) and alarm. these complementary but distinct functions share a common interface in a single package. although monolithic, the product is organized as two logical devices, the f-ram memory and the rtc/alarm. from the system perspective, they appear to be two separate devices with unique ids on the serial bus. the memory is organized as a stand-alone 2-wire nonvolatile memory with a standard device id value. the real-time clock and alarm are accessed with a separate 2-wire device id. this allows clock/calendar data to be read while maintaining the most recently used memory address. the clock and alarm are controlled by 15 special function registers. the registers are maintained by the power source on the vbak pin, allowing them to operate from battery or backup capacitor power when v dd drops below a set threshold. each functional block is described below. memory operation the fm3130 integrates a 64kb f-ram. the memory is organized in bytes, 8192 addresses of 8 bits each. the memory is based on f-ram technology. therefore it can be treated as ram and is read or written at the speed of the two-wire bus with no delays for write operations. it also offers effectively unlimited write endurance unlike other nonvolatile memory technologies. the two-wire interface protocol is described further on page 12. the memory array can be write-protected by software. two bits (wp0, wp1) in register 0eh control the protection setting as shown in the following table. based on the setting, the protected addresses cannot be written and the 2-wire interface will not acknowledge any data to protected addresses. the special function registers containing these bits are described in detail below. table 1. f-ram write-protect write-protect range wp1 wp0 none 0 0 bottom 1/4 0 1 bottom 1/2 1 0 full array 1 1 the wp bits are battery-backed. on a powerup without a backup source, the wp bits are cleared to a ?0? state. real-time clock operation the real-time clock (rtc) is a timekeeping device that can be battery or capacitor backed for permanently-powered operation. it offers a software calibration feature that allows high accuracy. the rtc consists of an oscillator, clock divider, and a register system for user access. it divides down the 32.768 khz time-base and provides a minimum resolution of seconds (1hz). static registers provide the user with read/write access to the time values. it includes registers for seconds, minutes, hours, day- of-the-week, date, months, and years. a block diagram (figure 2) illustrates the rtc function. the user registers are synchronized with the timekeeper core using r and w bits in register 00h described below. changing the r bit from 0 to 1 transfers timekeeping information from the core into holding registers that can be read by the user. if a timekeeper update is pending when r is set, then the core will be updated prior to loading the user registers. the registers are frozen and will not be updated again until the r bit is cleared to ?0?. r is used to read the time. setting the w bit to ?1? locks the user registers. clearing it to a ?0? causes the values in the user registers to be loaded into the timekeeper core. w is used for writing new time values. users should be certain not to load invalid values, such as ffh, to the timekeeping registers. updates to the timekeeping core occur continuously except when locked. all timekeeping registers must be initialized at the first powerup or when the lb bit is set. see the description of the lb bit on page 11. backup power the real-time clock/calendar is intended to be permanently powered. when the primary system power fails, the voltage on the v dd pin will drop. when v dd is less than v sw , the rtc will switch to the backup power supply on v bak . the clock operates at extremely low current in order to maximize battery or capacitor life. however, an advantage of combining a clock function with f- ram memory is that data is not lost regardless of the backup power source. if a battery is applied without a v dd power supply, the device has been designed to ensure the i bak current does not exceed the 1 a maximum limit. trickle charger to facilitate capacitor backup the v bak pin can optionally provide a trickle charge current. when the
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 4 of 22 vbc bit (register 0eh, bit 2) is set to a ?1?, the v bak pin will source approximately 80 a until v bak reaches v dd . this charges the capacitor to v dd without an external diode and resistor charger. there is a fast charge mode which is enabled by the fc bit (register 0eh, bit 1). in this mode the trickle charger current is set to approximately 1 ma, allowing a large backup capacitor to charge more quickly. ? in the case where no battery is used, the v bak pin should be tied to v ss . ! ! ! ! note: systems using lithium batteries should clear the vbc bit to 0 to prevent battery charging. the v bak circuitry includes an internal 1 k ? series resistor as a safety element. the trickle charger is ul recognized. figure 2. real-time clock core block diagram calibration when the cal bit in register 00h is set to ?1?, the clock enters calibration mode. in calibration mode, the acs output pin is dedicated to the calibration function and the power fail output is temporarily unavailable. calibration operates by applying a digital correction to the counter based on the frequency error. in this mode, the acs pin is driven with a 512 hz (nominal) square wave. any measured deviation from 512 hz translates into a timekeeping error. the user converts the measured error in ppm and writes the appropriate correction value to the calibration register. the correction factors are listed in the table below. positive ppm errors require a negative adjustment that removes pulses. negative ppm errors require a positive correction that adds pulses. positive ppm adjustments have the cals (sign) bit set to ?1?, whereas negative ppm adjustments have cals = 0. after calibration, the clock will have a maximum error of 2.17 ppm or 0.09 minutes per month at the calibrated temperature. the calibration setting is battery-backed and must be reloaded should the backup source fail. it is accessed with bits cal.4-0 in register 01h. this value only can be written when the cal bit is set to a ?1?. to exit the calibration mode, the user must clear the cal bit to a ?0?. when the cal bit is ?0?, the acs pin will revert to another function as defined in table 3. control bit settings for acs pin . crystal type the crystal oscillator is designed to use a 12.5pf crystal without the need for external components, such as loading capacitors. the fm3130 device has built-in loading capacitors that match the crystal. if a 32.768khz crystal is not used, an external oscillator may be connected to the fm3130. apply the oscillator to the x1 pin. its high and low voltage levels can be driven rail-to-rail or amplitudes as low as approximately 500mv p-p. to ensure proper operation, a dc bias must be applied to the x2 pin. it should be centered between the high and low levels on the x1 pin. this can be accomplished with a voltage divider. see figure 3. 32.768 khz crystal oscillato r cloc k divide r update logic 512 hz o r sw out w r seconds 7 bits minutes 7 bits hours 6 bits date 6 bits months 5 bits years 8 bits days 3 bits user interface registers 1 hz /oscen cf
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 5 of 22 figure 3. external oscillator in the example, r1 and r2 are chosen such that the x2 voltage is centered around the oscillator drive levels. if you wish to avoid the dc current, you may choose to drive x1 with an external clock and x2 with an inverted clock using a cmos inverter. layout recommendations the x1 and x2 crystal pins employ very high impedance circuits and the oscillator connected to these pins can be upset by noise or extra loading. to reduce rtc clock errors from signal switching noise, a guard ring should be placed around these pads and the guard ring grounded. sda and scl traces should be routed away from the x1/x2 pads. the x1 and x2 trace lengths should be less than 5 mm. the use of a ground plane on the backside or inner board layer is preferred. see layout example. red is the top layer, green is the bottom layer. layout for surface mount crystal layout for through hole crystal (red = top layer, green = bottom layer) (red = top layer, green = bottom layer) table 2. calibration adjustments positive calibration for slow clocks: calibration will achieve 2.17 ppm after calibration measured frequency range error range (ppm) min max min max program calibration register to: 0 512.0000 511.9989 0 2.17 000000 1 511.9989 511.9967 2.18 6.51 100001 2 511.9967 511.9944 6.52 10.85 100010 3 511.9944 511.9922 10.86 15.19 100011 4 511.9922 511.9900 15.20 19.53 100100 5 511.9900 511.9878 19.54 23.87 100101 6 511.9878 511.9856 23.88 28.21 100110 7 511.9856 511.9833 28.22 32.55 100111 8 511.9833 511.9811 32.56 36.89 101000 9 511.9811 511.9789 36.90 41.23 101001 10 511.9789 511.9767 41.24 45.57 101010 11 511.9767 511.9744 45.58 49.91 101011 12 511.9744 511.9722 49.92 54.25 101100 13 511.9722 511.9700 54.26 58.59 101101 14 511.9700 511.9678 58.60 62.93 101110 15 511.9678 511.9656 62.94 67.27 101111 16 511.9656 511.9633 67.28 71.61 110000 17 511.9633 511.9611 71.62 75.95 110001 18 511.9611 511.9589 75.96 80.29 110010 19 511.9589 511.9567 80.30 84.63 110011 20 511.9567 511.9544 84.64 88.97 110100 21 511.9544 511.9522 88.98 93.31 110101 22 511.9522 511.9500 93.32 97.65 110110 23 511.9500 511.9478 97.66 101.99 110111 x1 vd d fm3130 r1 r2 x1 x2 vbak vss x1 x2 vbak vss
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 6 of 22 24 511.9478 511.9456 102.00 106.33 111000 25 511.9456 511.9433 106.34 110.67 111001 26 511.9433 511.9411 110.68 115.01 111010 27 511.9411 511.9389 115.02 119.35 111011 28 511.9389 511.9367 119.36 123.69 111100 29 511.9367 511.9344 123.70 128.03 111101 30 511.9344 511.9322 128.04 132.37 111110 31 511.9322 511.9300 132.38 136.71 111111 negative calibration for fast clocks: calibration will achieve 2.17 ppm after calibration measured frequency range error range (ppm) min max min max program calibration register to: 0 512.0000 512.0011 0 2.17 000000 1 512.0011 512.0033 2.18 6.51 000001 2 512.0033 512.0056 6.52 10.85 000010 3 512.0056 512.0078 10.86 15.19 000011 4 512.0078 512.0100 15.20 19.53 000100 5 512.0100 512.0122 19.54 23.87 000101 6 512.0122 512.0144 23.88 28.21 000110 7 512.0144 512.0167 28.22 32.55 000111 8 512.0167 512.0189 32.56 36.89 001000 9 512.0189 512.0211 36.90 41.23 001001 10 512.0211 512.0233 41.24 45.57 001010 11 512.0233 512.0256 45.58 49.91 001011 12 512.0256 512.0278 49.92 54.25 001100 13 512.0278 512.0300 54.26 58.59 001101 14 512.0300 512.0322 58.60 62.93 001110 15 512.0322 512.0344 62.94 67.27 001111 16 512.0344 512.0367 67.28 71.61 010000 17 512.0367 512.0389 71.62 75.95 010001 18 512.0389 512.0411 75.96 80.29 010010 19 512.0411 512.0433 80.30 84.63 010011 20 512.0433 512.0456 84.64 88.97 010100 21 512.0456 512.0478 88.98 93.31 010101 22 512.0478 512.0500 93.32 97.65 010110 23 512.0500 512.0522 97.66 101.99 010111 24 512.0522 512.0544 102.00 106.33 011000 25 512.0544 512.0567 106.34 110.67 011001 26 512.0567 512.0589 110.68 115.01 011010 27 512.0589 512.0611 115.02 119.35 011011 28 512.0611 512.0633 119.36 123.69 011100 29 512.0633 512.0656 123.70 128.03 011101 30 512.0656 512.0678 128.04 132.37 011110 31 512.0678 512.0700 132.38 136.71 011111 alarm the alarm function compares user-programmed alarm values to the corresponding rtc time/date values. when a match occurs, an alarm event occurs. the alarm event sets an internal flag af (register 00h, bit 6) and drives the acs pin low, if the appropriate control bits are set in registers 00h and 0eh. see table 3. the alarm condition on the acs pin and the af bit are cleared by reading register 00h. the alarm operates under v dd or v bak power. if the system controller is being used to detect an alarm while the fm3130 is powered on v bak only, the acs pin may cause extra i bak current when the alarm is activated. to avoid battery drain, the acs pin can be tri-stated by reading the af flag, located in the rtc/alarm control register 00h. there are five alarm match fields. they are month, date, hours, minutes, and seconds. each of these fields also has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field will be used in the match process. depending on the match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once per second continuously. the msb of each alarm register is a match bit. examples of the match bit settings are shown in table 4. alarm match bit examples . selecting none of the match bits (all ?1?s) indicates that no match is required. the alarm occurs every
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 7 of 22 second. setting the match select bit for seconds to ?0? causes the logic to match the seconds alarm value to the current time of day. since a match will occur for only one value per minute, the alarm occurs once per minute. likewise setting the seconds and minutes match select bits causes an exact match of these values. thus, an alarm will occur once per hour. setting seconds, minutes, and hours causes a match once per day. see table 4 for other alarm setting examples. function of the acs pin the acs pin is a multifunction pin. the alarm, calibration, and square wave functions all share this output. there are two ways a user can detect an alarm event, by reading the af flag or by monitoring the acs pin. an interrupt pin on the host processor may be used to detect an alarm event. the af flag in the register 00h (bit 6) will indicate that a time/date match has occurred. when a match occurs, the af bit will be set to ?1? and the acs pin will drive low. the flag and acs pin will remain in this state until the rtc/alarm control register is read which clears the af bit. table 3 that shows the relationship between register control settings and the function of the acs pin. table 3. control bit settings for acs pin state of register bit function of acs pin cal aen al/sw 0 1 1 /alarm 0 x 0 sq wave out 1 x x 512 hz out 0 0 1 hi-z cal output/squarewave output when the rtc calibration mode is invoked by setting the cal bit (register 00h, bit 2), the acs output pin will be driven with a 512 hz square wave and the alarm will continue to operate. since most users only invoke the calibration mode during production, this should have no impact on the otherwise normal operation of the alarm. the acs output may also be used to drive the system with a continuous frequency. the al/sw bit (register 0eh, bit 7) must be a ?0?. a user-selectable frequency is provided by f0 and f1 (register 0eh, bits 5 and 6). the frequencies are 1, 512, 4096, and 32768 hz. if a continuous frequency output is enabled by using the 512hz or squarewave out functions, the alarm function will not be available. figure 4. acs pin requires pullup the acs pin is an open-drain output that needs to be pulled up to a supply. the acs pin and pullup resistor draws current only when the alarm is triggered. table 4. alarm match bit examples seconds minutes hours date months alarm condition 1 1 1 1 1 no match required = alarm 1/second 0 1 1 1 1 alarm when seconds match = alarm 1/minute 0 0 1 1 1 alarm when seconds, minutes match = alarm 1/hour 0 0 0 1 1 alarm when seconds, minutes, hours match = alarm 1/date 0 0 0 0 1 alarm when seconds, minutes, hours, date match = alarm 1/month acs 1m ? mcu fm3130 v bak
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 8 of 22 register map the rtc, alarm, and other functions are accessed via 15 special function registers mapped to a separate 2-wire device id. the interface protocol is described below. the registers contain timekeeping data, control bits, or information flags. a description of each register follows the summary table below. register map summary table address d7 d6 d5 d4 d3 d2 d1 d0 function range 0eh al/sw f1 f0 wp1 wp0 vbc fc tst alarm & wp control 0dh /match 0 0 10 mo alarm months alarm month 01-12 0ch /match 0 10 date alarm date alarm date 01-31 0bh /match 0 alarm 10 hours alarm hours alarm hours 00-23 0ah /match alarm 10 minutes alarm minutes alarm minutes 00-59 09h /match alarm 10 seconds alarm seconds alarm seconds 00-59 08h 10 years years rtc years 00-99 07h 00010 mo months rtc month 1-12 06h 00 10 date date rtc date 1-31 05h 00000 day rtc day 1-7 04h 00 10 hours hours rtc hours 0-23 03h 0 10 minutes minutes rtc minutes 0-59 02h 0 10 seconds seconds rtc seconds 0-59 01h /oscen - cals cal4 cal3 cal2 cal1 cal0 cal/control 00h lb af cf por aen cal w r rtc/alarm control note: when the device is first powered up, all registers should be treated as unknown and must be written. otherwise, unpredictable behavior may result.
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 9 of 22 register description address description 0eh alarm & wp control d7 d6 d5 d4 d3 d2 d1 d0 al/sw f1 f0 wp1 wp0 vbc fc tst al/sw alarm/square wave select: when set to 1, the alarm controls the acs pin as well as the af flag. when set to 0, the selected square wave freq will be driven on the acs pin, and an alarm match only sets the af flag. battery- backed, read/write. f(1:0) square wave freq select: these bits select the frequency on the acs pin when the cal and al/sw bits are both 0. battery-backed. setting f(1:0) setting f(1:0) 1 hz 00 (default) 4096 hz 10 5 12 hz 01 32768 hz 11 wp1,wp0 write protect. these bits control the write protection of the memory array. battery-backed, read/write. write-protect addresses wp1 wp0 none 0 0 bottom 1/4 0 1 bottom 1/2 1 0 full array 1 1 vbc vbak charger control: setting vbc to 1 (and fc=0) causes approx. 80 a (1ma if fc=1) trickle charge current to be supplied on v ba k . clearing vbc to 0 disables the charge current. battery-backed, read/write. fc fast charge: setting fc to 1 (and vbc=1) causes approx. 1ma trickle charge current to be supplied on v bak . clearing vbc to 0 disables the charge current. battery-backed, read/write. tst invokes factory test mode. users should always set this bit to 0. 0dh alarm ? month d7 d6 d5 d4 d3 d2 d1 d0 m 0 0 10 month month.3 month.2 month.1 month.0 contains the alarm value for the month and the mask bit to select or deselect the month value. /m match. setting this bit to a ?0? causes the month value to be used in the alarm match logic. setting this bit to a ?1? causes the match circuit to ignore the month value. battery-backed, read/write. 0ch alarm ? date d7 d6 d5 d4 d3 d2 d1 d0 m 0 10 date.1 10 date.0 date.3 date.2 date.1 date.0 contains the alarm value for the date and the mask bit to select or deselect the date value. /m match: setting this bit to a ?0? causes the date value to be used in the alarm match logic. setting this bit to a ?1? causes the match circuit to ignore the date value. battery-backed, read/write. 0bh alarm ? hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10 hours.1 10 hours.0 hours.3 hours2 hours.1 hours.0 contains the alarm value for the hours and the mask bit to select or deselect the hours value. /m match: setting this bit to a ?0? causes the hours value to be used in the alarm match logic. setting this bit to a ?1? causes the match circuit to ignore the hours value. battery-backed, read/write. 0ah alarm ? minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10 min.2 10 min.1 10 min.0 min.3 min.2 min.1 min.0 contains the alarm value for the minutes and the mask bit to select or deselect the minutes value /m match: setting this bit to a ?0? causes the minutes value to be used in the alarm match logic. setting this bit to a ?1? causes the match circuit to ignore the minutes value. battery-backed, read/write.
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 10 of 22 09h alarm ? seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10 sec.2 10 sec.1 10 sec.0 seconds.3 seconds.2 seconds.1 seconds.0 contains the alarm value for the seconds and the mask bit to select or deselect the seconds value. /m match: setting this bit to a ?0? causes the seconds value to be used in the alarm match logic. setting this bit to a ?1? causes the match circuit to ignore the seconds value. battery-backed, read/write. 08h timekeeping ? years d7 d6 d5 d4 d3 d2 d1 d0 10 year.3 10 year.2 10 year.1 10 year.0 year.3 year.2 year.1 year.0 contains the lower two bcd digits of the year. lower nibble contains the value for years; upper nibble contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0-99. battery-backed, read/write. 07h timekeeping ? months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10 month month.3 month.2 month.1 month.0 contains the bcd digits for the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the register is 1-12. battery- backed, read/write. 06h timekeeping ? date of the month d7 d6 d5 d4 d3 d2 d1 d0 0 0 10 date.1 10 date.0 date.3 date.2 date.1 date.0 contains the bcd digits for the date of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. the range for the register is 1-31. battery-backed, read/write. 05h timekeeping ? day of the week d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day.2 day.1 day.0 lower nibble contains a value that correlates to day of the week. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, as the day is not integrated with the date. battery-backed, read/write. 04h timekeeping ? hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10 hours.1 10 hours.0 hours.3 hours2 hours.1 hours.0 contains the bcd value of hours in 24-hour format. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0-23. battery-backed, read/write. 03h timekeeping ? minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10 min.2 10 min.1 10 min.0 min.3 min.2 min.1 min.0 contains the bcd value of minutes. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. the range for the register is 0-59. battery-backed, read/write. 02h timekeeping ? seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10 sec.2 10 sec.1 10 sec.0 seconds.3 seconds.2 seconds.1 seconds.0 contains the bcd value of seconds. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. the range for the register is 0-59. battery-backed, read/write. 01h cal/control d7 d6 d5 d4 d3 d2 d1 d0 oscen - cals cal.4 cal.3 cal.2 cal.1 cal.0 /oscen oscillator enable. when set to 1, the oscillator is halted. when set to 0, the oscillator runs. disabling the oscillator can save battery power during storage. on an initial power-up of v dd with or without v bak , this bit is internally set to 1, which turns off the oscillator. battery-backed, read/write.
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 11 of 22 cals calibration sign: determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. this bit can be written only when cal=1. battery-backed, read/write. cal.4-0 calibration code: these five bits control the calibration of the clock. these bits can be written only when cal=1. battery-backed, read/write. 00h rtc/alarm control d7 d6 d5 d4 d3 d2 d1 d0 lb af cf por aen cal w r lb low battery flag: if the v bak source drops to a voltage level insufficient to operate the rtc/alarm, this bit will be set to ?1?. all registers need to be re-initialized since the battery-backed register values should be treated as unknown. the user should clear it to ?0? when initializing the system. battery-backed. read/write (internally set, user can clear bit by writing to a ?0?). af alarm flag: this read-only bit is set to 1 when the time/date match the values stored in the alarm registers with the match bit(s) = 0. it is cleared when the rtc/alarm control register is read. battery-backed. cf century overflow flag: this read-only bit is set to a 1 when the values in the years register overflows from 99 to 00. this indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. the user should record the new century information as needed. this bit is cleared when the rtc/alarm control register is read. battery-backed. por power on reset flag: when v dd drops below v sw , the por bit will be set to ?1?. battery-backed. read/write (internally set, user can clear bit by writing to a ?0?). aen alarm enable: this bit enables the alarm function. when aen is set (and cal cleared), the acs pin operates as an active-low alarm and the af flag function is enabled. the function of the acs pin is detailed in table 3. when aen is cleared, no new alarm events will occur but the af flag and acs pin will not be cleared. battery-backed, read/write. cal calibration mode: when cal is set to ?1?, the clock enters calibration mode. when cal is set to ?0?, the clock operates normally, and the acs pin is controlled by the rtc alarm. battery-backed, read/write. w write rtc: setting the w bit to ?1? freezes updates of the user timekeeping registers. the user can then write them with updated values. setting the w bit to ?0? causes the contents of the time registers to be transferred to the timekeeping counters. battery-backed, read/write. r read rtc: setting the r bit to ?1? copies a static image of the timekeeping core and place it into the user registers. the user can then read them without concerns over changing values causing system errors. the r bit going from ?0? to ?1? causes the timekeeping capture, so the bit must be returned to ?0? prior to reading again. battery-backed, read/write.
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 12 of 22 two-wire interface the fm3130 employs an industry standard two-wire bus that is familiar to many users. this product is unique since it incorporates two logical devices in one chip. each logical device can be accessed individually. although monolithic, it appears to the system software to be two separate products. one is a memory device. it has a slave address (slave id = 1010b) that operates the same as a stand-alone memory device. the second device is a real-time clock and alarm which have a unique slave address (slave id = 1101b). by convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm3130 is always a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions: start, stop, data bit, and acknowledge. the figure below illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electrical specifications section. stop (master) start (master) 7 data bits (transmitter) 6 0 data bit (transmitter) acknowledge (receiver) scl sda figure 4. data transfer protocol start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all read and write transactions begin with a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm3130 for a new operation. stop condition a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations must end with a stop condition. if an operation is pending when a stop is asserted, the operation will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the two conditions described above, the sda signal should not change while scl is high. acknowledge the acknowledge (ack) takes place after the 8 th data bit has been transferred in any transaction. during this state the transmitter must release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no-acknowledge (nack) and the operation is aborted. the receiver might nack for two distinct reasons. first is that a byte transfer fails. in this case, the nack ends the current operation so that the part can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not send an ack to deliberately terminate an operation. for example, during a read operation, the fm3130 will continue to place data onto the bus as long as the receiver sends acks (and clocks). when a read operation is complete and no more data is needed, the receiver must nack the last byte. if the receiver acks the last byte, this will cause the fm3130 to attempt to drive the bus on the next clock while the master is sending a new command such as a stop. slave address the first byte that the fm3130 expects after a start condition is the slave address. as shown in figures below, the slave address contains the slave id and a bit that specifies if the transaction is a read or a write.
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 13 of 22 the fm3130 has two slave addresses (slave ids) associated with two logical devices. to access the memory device, bits 7-4 should be set to 1010b. the other logical device within the fm3130 is the real- time clock and alarm. to access this device, bits 7-4 of the slave address should be set to 1101b. a bus transaction with this slave address will not affect the memory in any way. the figures below illustrate the two slave addresses. bits 3 through 1 of the slave address must be logic 0. bit 0 is the read/write bit. a ?1? indicates a read operation, and a ?0? indicates a write operation. figure 5. slave address ? memory figure 6. slave address ? rtc addressing overview ? memory after the fm3130 acknowledges the slave address, the master can place the memory address on the bus for a write operation. the address requires two bytes. the first is the msb (upper byte). the first 3 unused address bits are don?t cares, but should be set to ?0? to maintain upward compatibility. following the msb is the lsb (lower byte) which contains the remaining eight address bits. the address is latched internally. each access causes the latched address to be incremented automatically. the current address is the value that is held in the latch, either a newly written value or the address following the last access. the current address will be held as long as v dd is greater than v sw or until a new value is written. accesses to the clock do not affect the current memory address. reads always use the current address. a random read address can be loaded by beginning a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm3130 increments the internal address. this allows the next sequential byte to be accessed with no additional addressing externally. after the last address is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. addressing overview ? rtc/alarm the rtc/alarm operates in a similar manner to the memory, except that it uses only one byte of address. addresses 00h to 0eh correspond to the rtc/alarm and control registers. attempting to load addresses above 0eh is an illegal condition; the fm3130 will return a nack and abort the 2-wire transaction. data transfer after the address information has been transmitted, data transfer between the bus master and the fm3130 begins. for a read, the fm3130 will place 8 data bits on the bus then wait for an ack from the master. if the ack occurs, the fm3130 will transfer the next byte. if the ack is not sent, the fm3130 will end the read operation. for a write operation, the fm3130 will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory write operation all memory writes begin with a slave address, then a memory address. the bus master indicates a write operation by setting the slave address lsb to a ?0?. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap to 0000h. internally, the actual memory write occurs after the 8 th data bit is transferred. it will be complete before the acknowledge is sent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using a start or stop condition prior to the 8 th data bit. the figures below illustrate a single- and multiple-writes to memory. 10 1 0 0 r/w slave id 76543 21 0 0 0 11 0 1 0 r/w slave id 76543 21 0 0 0
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 14 of 22 s a slave address 0 address msb a data byte a p by master by fm3130 start a ddress & data stop a cknowledge a ddress lsb a figure 7. single byte memory write s a slave address 0 address msb a data byte a p by master by fm3130 start address & data stop acknowledge address lsb a data byte a figure 8. multiple byte memory write memory read operation there are two types of memory read operations. they are current address read and selective address read. in a current address read, the fm3130 uses the internal address latch to supply the address. in a selective read, the user performs a procedure to first set the address to a specific value. current address & sequential read as mentioned above the fm3130 uses an internal latch to supply the address for a read operation. a current address read uses the existing value in the address latch as a starting place for the read operation. the system reads from the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to 1. this indicates that a read operation is requested. after receiving the complete device address, the fm3130 will begin shifting data out from the current address on the next clock. the current address is the value held in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. each time the bus master acknowledges a byte, this indicates that the fm3130 should read out the next sequential byte. there are four ways to terminate a read operation. failing to properly terminate the read will most likely create a bus contention as the fm3130 attempts to read out additional data onto the bus. the four valid methods follow. 1. the bus master issues a nack in the 9 th clock cycle and a stop in the 10 th clock cycle. this is illustrated in the diagrams below and is preferred. 2. the bus master issues a nack in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. 4. the bus master issues a start in the 9 th clock cycle. if the internal address reaches the top of memory, it will wrap around to 0000h on the next read cycle. the figures below show the proper operation for current address reads. selective (random) read there is a simple technique that allows a user to select a random address location as the starting point for a read operation. this involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb set to 0. this specifies a write operation. according to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. after the fm3130 acknowledges the address, the bus master
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 15 of 22 issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address lsb set to a ?1?. the operation is now a read from the current address. read operations are illustrated below. rtc/alarm write operation all rtc/alarm writes operate in a similar manner to memory writes. the distinction is that a different device id is used and only one byte address is needed instead of two. figure 12 illustrates a single byte write to the rtc/alarm. rtc/alarm read operation as with writes, a read operation begins with the slave address. to perform a register read, the bus master supplies a slave address with the lsb set to a ?1?. this indicates that a read operation is requested. after receiving the complete slave address, the fm3130 will begin shifting data out from the current register address on the next clock. auto-increment operates for the special function registers as with the memory address. a current address read for the registers look exactly like the memory except that the device id is different. the fm3130 contains two separate address registers, one for the memory address and the other for the register address. this allows the contents of one address register to be modified without affecting the current address of the other register. for example, this would allow an interrupted read to the memory while still providing fast access to an rtc register. a subsequent memory read will then continue from the memory address where it previously left off, without requiring the load of a new memory address. however, a write sequence always requires an address to be supplied. s a slave address 1 data byte 1 p by master by fm3130 start a ddress stop a cknowledge no a cknowledge data figure 9. current address memory read s a slave address 1 data byte 1 p by master by fm3130 start address stop acknowledge no a cknowledge data data byte a acknowledge figure 10. sequential memory read s a slave address 1 data byte 1 p by master by fm3130 start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a figure 11. selective (random) memory read
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 16 of 22 figure 12. register byte write * although not required, it is recommended that a7-a4 in the register address byte are zeros in order to preserve compatibility with future devices. s a slave address 0 a data byte a p by master start address & data stop acknowledge 000 by fm3130 0 address
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 17 of 22 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +5.0v v in voltage on any signal pin with respect to v ss -1.0v to +5.0v * and v in v dd +1.0v ** v bak backup supply voltage -1.0v to +4.5v t stg storage temperature -55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 300 c v esd electrostatic discharge voltage - human body model (jedec std jesd22-a114-b) - charged device model (jedec std jesd22-c101-a) - machine model (jedec std jesd22-a115-a) 4kv 1kv 200v package moisture sensitivity level msl-1 ** the ?v in < v dd +1.0v? restriction does not apply to the scl, sda, and acs pins which do not employ a diode to v dd . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly, and the functional operation of the device at these or any other conditions above those listed in the operational section of th is specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions ( t a = -40 c to + 85 c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd main power supply 2.7 - 3.6 v 1 i dd v dd supply current @ scl = 100 khz @ scl = 1 mhz 150 500 a a 2 i sb standby current trickle charger off (vbc=0) trickle chrg on, fast chrg off (vbc=1, fc=0) trickle chrg on, fast chrg on (vbc=1, fc=1) 50 190 2600 a a a 3 v bak rtc backup supply voltage 2.0 3.0 3.6 v 4 i bak rtc backup supply current 1 a a 6 i li input leakage current 1 1 notes 1. full complete operation. rtc operates to lower voltages as specified. 2. scl toggling between v dd -0.3v and v ss , other inputs v ss or v dd -0.3v. vbc=0. i dd is linear vs frequency. 3. all inputs at v ss or v dd, static. stop command issued. 4. the vbak trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 5. v bak = 3.0v, v dd < v sw , oscillator running. 6. v bak will source current when the trickle charger is enabled (vbc=1), v dd > v bak and v dd > v sw . 7. v in or v out = v ss to v dd .
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 18 of 22 ac parameters (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v, c l = 100 pf unless otherwise specified) symbol parameter min max min max min max units notes f scl scl clock frequency 0 100 0 400 0 1000 khz t low clock low period 4.7 1.3 0.6 supervisor timing (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v) symbol parameter min max units notes t vr v dd rise time 50 - capacitance (t a = 25 c, f=1.0 mhz, v dd = 3.0v) symbol parameter typ max units notes c io input/output capacitance - 8 pf 1 c xtl x1, x2 crystal pin capacitance 25 - pf 1, 3 notes 1 this parameter is characterized but not tested. 2 slope measured at any point on v dd waveform. 3 the crystal attached to the x1/x2 pins must be rated as 12.5pf. data retention (v dd = 2.7v to 3.6v) symbol parameter min units notes t dr data retention @ +75c @ +80c @ +85c 45 20 10 years years years
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 19 of 22 ac test conditions equivalent ac test load circuit input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagram notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters apply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant data sheet sections. these diagrams illustrate the timing parameters only. read bus timing t su:sta start t r ` t f stop start t buf t high 1/f scl t low t sp t sp acknowledge t hd:dat t su:dat t aa t dh scl sda write bus timing t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda power cycle timing vdd 2.7v can user access device? t rpu yes no yes 3.6v output 1100 ? 100 pf
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 20 of 22 mechanical drawing 8-pin soic (jedec standard ms-012 variation aa) pin 1 3.90 0.10 6.00 0.20 4.90 0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45 0.40 1.27 0.19 0.25 0 - 8 recommended pcb footprint 7.70 0.65 1.27 2.00 3.70 refer to jedec ms-012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxx= part number, p= package type lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm3130, ?green? soic package, year 2006, work week 24 fm3130-g a60003g ric0624 xxxxxxx-p lllllll ricyyww
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 21 of 22 8-pin tdfn (3.0 mm x 6.4 mm body, 0.65mm pitch) pin 1 6.40 0.1 3.00 0.1 0.75 0.05 0.25 0.05 0.65 0.20 ref. pin 1 id 0.0 - 0.05 exposed metal pad. do not connect to anything, except vss. 6.70 0.30 0.65 recommended pcb footprint 0.40 0.1 0.60 3.10 1.10 3.00 0.10 1.00 0.10 1.95 ref note: all dimensions in millimeters . this package is footprint compatible with the 8-pin tssop, however care must be taken to ensure pcb traces and vias are not placed within the exposed metal pad area. tdfn package marking scheme for body size 3mm x 6.4mm legend: r=ramtron int?l corp, g=?green? tdfn package xxxx=base part number llll= lot code yy=year, ww=work week example: ?green? tdfn package, fm3130, lot 0003, year 2006, work week 33 rg 3130 0003 0633 rg xxxx llll yyww
fm3130 integrated rtc/alarm with 64kb fram rev. 3.1 feb. 2009 page 22 of 22 revision history revision date summary 0.0 12/14/05 initial release. 0.1 2/28/06 all register space is battery-backed. moved location of some bits in regs 00 and 01h. removed serial number. added lb and por flags, and fast charge mode to trickle charger. industrial temp grade. 0.2 5/10/06 updated aen, af, and acs pin descriptions and backup power section. changed trickle charger limits and added v sw parameter. added tdfn package. 1.0 9/18/06 changed to preliminary status. changed i baktc (fc=0) from 50 to 25

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